Integrated circuit design typically begins with the knowledge of a design goal or specification. Such specifications describe the required performance of the circuit(s) to be designed. Integrated circuit designers typically first create a computer model of a circuit design that will meet the performance specification. That circuit design model is based upon the electrical circuit elements that are available in a given semiconductor manufacturing process. For example, electrical circuit elements may include diodes, transistors, capacitors, resistors, and so on. Typical modern integrated circuits include both p-channel and n-channel field effect transistors.
As is known in the field of integrated circuit design, the cost of preparing masks and fabricating the integrated circuits is very high. In view of these costs, integrated circuit designers perform extensive simulations of their circuit designs in order to reduce the risk of manufacturing a circuit that does not perform as desired. Such circuit simulations generally rely on four sets of information: (a) a network topology description, (b) circuit element models, (c) process related targets (e.g., transistor threshold voltages), and (d) input waveforms to drive the circuit being simulated.
Both the network topology description and the input waveforms are independent of, or at least substantially decoupled from, the semiconductor manufacturing process with which the circuit is intended to be manufactured. The circuit element models and the process related targets are closely related to this semiconductor manufacturing process.
It is common for integrated circuit designers to seek to reduce the static power consumed by integrated circuits. It is common in semiconductor process technology nodes from about 45 nm and beyond, that a substantial amount of static power is attributable to off-state leakage current in transistors. However, even in seeking to reduce the power consumption due to leakage current, designers also seek to re-use their circuit designs (both transistor network topologies and physical layout).
It is noted that the cross-sectional representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures, process steps, and operations which they are illustrating.